4. Explain the recent development of hardware and software technologies

A) Software development

The new servers T5 and M5 SPARC

Oracle founder and CEO Larry Ellison said that the SPARC T5 is the world's fastest microprocessor and that the new SPARC T5-based systems set 17 world records on industry-standard benchmarks. The new systems deliver dramatically better performance than the IBM Power Series. On the single-node TPC-C, benchmark, the SPARC T5-8 beat IBM Power 770 and 780 and delivered the highest result of any single server in the world.

The SPARC M5-32 server delivers massive system scalability and performance with up to 32 SPARC M5 processors and 32 TB of system memory. It offers the most comprehensive virtualization technologies in a single-server cabinet for increased utilization, server consolidation, and security. The SPARC M5-32 also supports, at no extra cost, Oracle’s Dynamic Domains, Oracle VM Server for SPARC, and the Oracle Solaris Zones feature.

Building on the success of its SPARC T4 servers, Oracle has now completely refreshed its SPARC server family. The new SPARC T5 servers extend the current portfolio of T4 servers, and are targeted at midrange computing, while the massively scalable SPARC M5-32 is the company's new mainframe-class system.

At the top end of the new M5 server portfolio is the M5-32 server. 32 M5 processors fit into the server, each with a six-core, 3.6 GHz SPARC processor. The M5 has a 48 MB Level 3 cache on each chip, and in total the M5-32 server system can provide 32 TB of memory and deliver 1,536 processor threads of throughput.

B) Hardware development

The zEnterprise BC12

The zBC12 is powered by up to 18 microprocessors, running at 4.2 GHz, boasting up to 36 percent improvement in performance per core, 58 percent more general system processing capacity and up to 62 percent more.

Data Sheet - IBM Systems and Technology

Total capacity compared to its predecessor, the z114.1 It also offers up to 496 GB of available memory (2X more than z114) to dramatically improve performance of memory constrained workloads. Each core on the zBC12 microprocessor chip has dedicated data compression and cryptographic processors improvement over the previous generation where two cores shared those processors. IBM continues to enhance IBM z/Architecture® with memory hierarchy improvements enabled by IBM z Systems™ chip designs, refinements in execution processing, and improved prefetch instructions all designed to optimize throughput for many workloads including those using Java and IBM DB2® for z/OS®. Improved performance is also achieved with system memory management overhead reduction through IBM z/OS enhancements combined with zBC12 hardware support for 2 GB pages. These advantages are expected to be especially useful for industries like financial markets where applications are continually refreshed. The zBC12 microprocessor chip has been optimized for software performance. With a redesign of cache, there are almost 2X the amount of cache on the chip and 2X the amount in the processor drawer than the prior generation. With a larger cache structure, there is less of a need to access main memory which helps improve the performance of data serving. The zBC12 microprocessor also includes multiple innovative architectures that will allow new software paradigms to be deployed on the platform. The zBC12 supports a general purpose hardware transactional memory architecture called Transactional Execution. It is included in the firmware and initially the chief exploiter is Java. Transactional Execution helps eliminate tension between locks for workloads running.